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CY7C1061AV33
16-Mbit (1M x 16) Static RAM
Features
* High speed -- tAA = 10 ns * Low active power -- 990 mW (max) * Operating voltages of 3.3 0.3V * 2.0V data retention * Automatic power down when deselected * TTL compatible inputs and outputs * Easy memory expansion with CE1 and CE2 features * Available in Pb-free and non Pb-free 54-pin TSOP II package and non Pb-free 60-ball fine pitch ball grid array (FBGA) package
Functional Description
The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, enable the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19). To read from the device, enable the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory will appear on IO8 to IO15. See "Truth Table" on page 7 for a complete description of Read and Write modes. The input/output pins (IO0 through IO15) are placed in a high-impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a Write operation is in progress (CE1 LOW, CE2 HIGH, and WE LOW).
Logic Block Diagram
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
SENSE AMPS
1M x 16 ARRAY
IO0-IO7 IO8-IO15
COLUMN DECODER
A10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A18 A19
BHE WE OE BLE
CE2 CE1
Cypress Semiconductor Corporation Document #: 38-05256 Rev. *G
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 26, 2007
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CY7C1061AV33
Selection Guide
-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/Industrial 10 275 275 50 -12 12 260 260 50 mA Unit ns mA
Pin Configurations [1, 2]
60-ball FBGA Top View 4 3
54-pin TSOP II (Top View)
1
2
5
6
NC NC
NC
NC
NC NC
BLE IO 8 IO 9 VSS VCC IO 14
OE BHE IO 10 IO11 IO 12 IO 13
A0 A3 A5 A17 NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CE1 IO 1 IO 3 IO 4 IO 5 WE A11
CE2 IO 0 IO 2 VCC VSS IO 6 IO 7 A19
A B C D E F G H
IO 15 DNU A18 A8
IO 12 VCC IO 13 IO 14 VSS IO 15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 IO 0 VCC IO 1 IO 2 VSS IO 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
IO 11 VSS IO 10 IO 9 VCC IO 8 A5 A6 A7 A8 A9 NC OE VSS DNU BLE A10 A11 A12 A13 A14 IO 7 VSS IO 6 IO 5 VCC IO 4
NC NC NC NC
NC NC
Notes 1. NC pins are not connected on the die. 2. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper operation.
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CY7C1061AV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND [3] ... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State [3] ...................................-0.5V to VCC + 0.5V
DC Input Voltage [3] ............................... -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 0.3V
DC Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage
[3]
Test Conditions IOH = -4.0 mA IOL = 8.0 mA
-10 Min 2.4 0.4 2.0 -0.3 -1 -1 VCC + 0.3 0.8 +1 +1 275 275 70 2.0 -0.3 -1 -1 Max Min 2.4
-12 Max 0.4 VCC + 0.3 0.8 +1 +1 260 260 70
Unit V V V V A A mA mA mA
Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current Automatic CE Power-down Current --TTL Inputs Automatic CE Power-down Current --CMOS Inputs VCC = max, f = fmax = 1/tRC Commercial Industrial
CE2 <= VIL, max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fmax CE2 <= 0.3V Commercial/ Industrial max VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
ISB2
50
50
mA
Capacitance [4]
Parameter CIN COUT Description Input Capacitance IO Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V TSOP II 6 8 FBGA 8 10 Unit pF pF
AC Test Loads and Waveforms [5]
50 OUTPUT Z0 = 50 VTH = 1.5V 30 pF* * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 90% 10% 90% 10% Fall time: > 1V/ns 3.3V OUTPUT 5 pF* INCLUDING JIG AND SCOPE (b) R2 351 R1 317
(a)
3.3V GND
Rise time > 1V/ns
(c)
Notes 3. VIL (min) = -2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
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CY7C1061AV33
AC Switching Characteristics (Over the Operating Range) [6]
Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW
[10, 11]
Description
-10 Min 1 10 10 3 10 5 1 1 5
[8] [8]
-12 Max Min 1 12 12 3 12 6 6 3 5 6 0 10 5 12 6 1 5 6 12 8 8 0 0 8 6 0 3 5 6 8 Max
Unit
VCC(typical) to the first access [7] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW/CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z
[8]
ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW/CE2 HIGH to Low-Z CE1 HIGH/CE2 LOW to High-Z
3 0
[9]
CE1 LOW/CE2 HIGH to Power Up [9] CE1 HIGH/CE2 LOW to Power Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z Write Cycle Time CE1 LOW/CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low-Z WE LOW to High-Z
[8] [8]
1
10 7 7 0 0 7 5.5 0 3 7
Byte Enable to End of Write
Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the "AC Test Loads and Waveforms [5]" on page 3, unless specified otherwise. 7. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. tpower time must be provided initially before a Read/Write operation is started. 8. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of "AC Test Loads and Waveforms [5]" on page 3. Transition is measured 200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY7C1061AV33
Data Retention Waveform
DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [12, 13]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled) [13, 14]
ADDRESS tRC CE1 CE2 tACE BHE/BLE tDBE tLZBE OE tDOE DATA VALID tHZOE HIGH IMPEDANCE tHZBE tPD tHZCE
DATA OUT
tLZOE HIGH IMPEDANCE tLZCE
VCC SUPPLY CURRENT
tPU
50%
50%
ICC ISB
Notes 12. Device is continuously selected. OE, CE, BHE or BHE, or both = VIL. CE2 = VIH. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
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CY7C1061AV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled) [15, 16]
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA
WE
BHE/BLE
tBW
OE tSD DATA IO NOTE 17 tHZOE VALID DATA tHD
Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16]
tWC ADDRESS tSCE CE1 CE2
BHE/BLE tAW tSA WE
tBW
tHA tPWE
tSD DATA IO NOTE 17 VALID DATA
tHD
tHZWE
Notes 15. Data IO is high impedance if OE, or BHE or BLE or both = VIH. 16. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 17. During this period, the IOs are in output state and input signals should not be applied.
tLZWE
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CY7C1061AV33
Switching Waveforms (continued)
Write Cycle No. 3 (BHE/BLE Controlled)
tWC ADDRESS
CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 17 VALID DATA tHD tBW tHA
Truth Table
CE1 H X L L L L L L L CE2 X L H H H H H H H OE X X L L L X X X H WE X X H H H L L L H BLE X X L L H L L H X BHE X X L H L L H L X IO0-IO7 High-Z High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z IO8-IO15 High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power Down Power Down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
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CY7C1061AV33
Ordering Information
Speed (ns) 10 Ordering Code CY7C1061AV33-10ZXC CY7C1061AV33-10BAC CY7C1061AV33-10ZI CY7C1061AV33-10ZXI CY7C1061AV33-10BAXI CY7C1061AV33-12ZC CY7C1061AV33-12ZXC CY7C1061AV33-12BAC CY7C1061AV33-12ZXI Package Diagram 51-85160 51-85162 51-85160 51-85162 51-85160 51-85162 51-85160 Package Type 54-pin TSOP II (Pb-free) 60-ball FBGA 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball FBGA (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball FBGA 54-pin TSOP II (Pb-free) Operating Range Commercial Industrial
12
Commercial
Industrial
Contact local Cypress representative for availability of the these parts.
Package Diagrams
Figure 1. 54-pin TSOP II, 51-85160
51-85160-**
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CY7C1061AV33
Package Diagrams (continued)
Figure 2. 60-ball FBGA (8 x 20 x 1.2 mm), 51-85162
TOP VIEW A1 CORNER BOTTOM VIEW A1 CORNER 6 5 4 3 2 1 DUMMY BALL (0.3) X12
1
2
3
4
5
6
O0.05 M C O0.25 M C A B O0.300.05(48X)
A B C 20.000.10 18.00 2.625 D 20.000.10 E F G H A B C D 0.75 E F G H
5.25
DIMENSIONS IN MM
0.75
PART #
1.00
BA60A
1.875 0.75 0.75 1.00 3.75
STANDARD PKG. LEAD FREE PKG.
A B 8.000.10 A
BK60A
PKG WEIGHT: 0.30 gms
0.530.05
0.25 C
0.210.05
6.00 0.15 C
B 0.15(4X)
8.000.10
SEATING PLANE 0.36 C 1.20 MAX
51-85162-*D
All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1061AV33
Document History Page
Document Title: CY7C1061AV33 16-Mbit (1M x 16) Static RAM Document Number: 38-05256 REV. ** *A *B ECN NO. 113725 117058 117989 Issue Date 03/28/02 07/31/02 08/30/02 Orig. of Change NSL DFP DFP New Data Sheet Removed 15-ns bin Added 8-ns bin Changed Icc for 8, 10, 12 bins tpower changed from 1 s to 1 ms. Load Cap Comment changed (for Tx line load) tSD changed to 5.5 ns for the 10-ns bin Changed some 8-ns bin numbers (tHZ, tDOE, tDBE) Removed hz*C
120383
11/06/02
DFP
*D *E
124439 492137
2/25/03 See ECN
MEG NXR
*F *G
508117 877322
See ECN See ECN
NXR VKN
Document #: 38-05256 Rev. *G
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